The present invention relates to microprocessor based systems, and more particularly to reducing power consumption in a microprocessor.
Advances in semiconductor fabrication technology have given rise to considerable increases in clock speeds and significant decreases in die sizes of microprocessor-based System-on-chip (SoC) semiconductors. As a result, heat buildup in SoCs has become a significant problem in the semiconductor industry. There is an industry wide need to find ways to reduce power consumption, especially for SoC semiconductors.
An SoC may include a microprocessor. The load/store unit (LSU) of such a microprocessor is responsible for continually providing data to the execution unit of the microprocessor. To reduce latency, a conventional LSU typically employs one or more levels of high-speed cache memory. While conventional caches work for their intended purpose, they consume a significant portion of the total power used by a microprocessor and generate an undesirable amount of heat. This makes microprocessors having conventional data caches undesirable and/or impractical for many SoC-based applications.
What is needed is a microprocessor with a data cache system that offers the performance advantages of a large low-latency cache but consumes less power.